Latching fuse state storage circuits (fuse latch circuits) are used to store apparatus-relevant information, such as e.g. the state of a fuse, or repair information for memory chips. Latching fuse state stores (fuse latches) are exposed to the influence of errors that can be rectified, to a disturbance mechanism which is caused by particles, in particular α particles, which penetrate through the active state storage area and alter the state of the state store.
This represents a serious problem since the apparatus may be in operation for an indeterminate length of time and the error (incorrect stored state of the fuse to be monitored) is not corrected since the state stores (latches) are only set during the run-up or during the start of the apparatus. Module-relevant information, such as the repair information, is lost and cannot be recovered while the apparatus is active. Even more important is the fact that errors which [lacuna] by such state stores (latches) that have changed over unintentionally are difficult to detect. In present-day designs, the setting of the state store (set a fuse latch) is a “global” operation, which means that all the state stores (fuse latches) are set simultaneously. Therefore, it is not possible to refresh the state store information while the apparatus is active.
The problem has been alleviated hitherto by derating a state storage circuit (fuse latch circuit). This reduces the probability of an error occurring, but ultimately does not solve the problem.
FIG. 1 illustrates a customary state storage circuit. A supply voltage 1 (VDD) is connected via a first switching device 23, in particular a field-effect transistor, to an actual state store 3 (fuse latch), which has two inverters I. The first switching device 23 is actuated by a first drive signal 5 (FPUP). Via a connection 16, the first switching device 23 is connected to a second switching device 24, which is actuated by a second drive signal 6 (FPUN). Located between the second switching device 24 and a ground terminal 2 is the fuse 4 whose state is monitored by the circuit in accordance with FIG. 1. In parallel with the connection 16 between the first switching device 23 and the second switching device 24, the two inverters I are connected in series, between the two inverters a signal branching off to a detection device 15, in particular a decoding device.
FIG. 2 shows the drive signals 5, 6 plotted against time in order to elucidate the method of operation of the arrangement according to FIG. 1. The drive signal 5 (FPUP), which is applied to the first switching device 23, controls the resetting (reset) of the state store 3. After the run-up, a low level signal at the switching device 23 effects a resetting 7 (reset) of the state store 3 (latch). The second drive signal 6 (FPUN) controls the setting (set) of the state store 3 (latch), in which case, in the event of a high level signal at the second switching device 24, the state store 3 (latch) is set 8 (set latch) in accordance with the state of the fuse 4, which may be intact or blown. This operation is effected only once in each case after the activation of the apparatus during the run-up sequence in the event of a start-up.